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RISC-V Pipeline Simulator
A cycle-accurate 5-stage pipeline simulator for the RISC-V instruction set architecture.
Project Diagram
About The Project
The RISC-V Pipeline Simulator is a C-based project that provides a cycle-accurate simulation of a 5-stage instruction pipeline for the RISC-V architecture. It includes logic for cache simulation, allowing for a detailed analysis of the performance of different cache configurations.
Key Features
- Cycle-Accurate Simulation: The simulator accurately models the behavior of the pipeline on a cycle-by-cycle basis.
- 5-Stage Pipeline: The simulator implements the five classic stages of a RISC pipeline: Fetch, Decode, Execute, Memory, and Writeback.
- Cache Simulation: The simulator includes a configurable cache simulator to study the impact of cache performance on the pipeline.
Technical Details
The simulator is written in C and is designed to be highly modular and extensible. The pipeline stages are implemented as separate modules, making it easy to modify and experiment with different pipeline configurations. The cache simulator is also a separate module that can be easily replaced with a different cache implementation.